High-Power Electronics - Chilab

High-Power Electronics

In the framework of successive collaborations with the company Vishay Semiconductor Italiana S.p.A., Schottky Barrier diodes (SBDs) were realized and characterized.

The diodes were fabricated on 4H-SiC n-type wafers with an epitaxial layer and a barrier metal-oxide overlap for electric field termination. Diodes with voltage breakdown ranging between 400V and 700V and ideality factor as low as 1.05 were obtained and tested.

In detail, the procedure for the realization of Schottky diodes on 4H-SiC is the following. We started with SiC wafers with a 7-mm thick lightly doped (10^15 cm^-3) n-type epi-layer grown on highly doped (10^19 cm^-3) Si-face 4H-SiC substrate, commercially available from Cree Researchand Si Crystal AG. The first processing step performed on the 4H-SiC substrates was the fabrication of a p-doped guard ring, using boron ion implantation. The implanted wafers were then annealed at temperatures exceeding 1550°C, using a Rapid Thermal Process (RTP), in order to obtain a full electrical activation of the boron ion dopants. A thin film of silicon dioxide was then grown on the epi-layer by Plasma Enhanced Chemical Vapour Deposition (PECVD) or by a low temperature oxidation process using TetraEthylOxySilane (TEOS) as precursor. The deposition conditions were chosen so as to optimize SiO2 insulating properties. After the growth of the silicon dioxide layer, the samples were patterned by standard UV photolithography in order to realize a metal overlap structure at the periphery of the diode. This structure is useful in order to prevent any electric field crowding at the contact edge. Schottky barrier formation on 4H-SiC epi-layer was then performed by thermal or electron beam-assisted evaporation. Titanium, nickel or molybdenum thin layers with or without thermal annealing in controlled atmosphere (under N2 flow) were used for the Schottky barrier. A thick aluminium film was grown on the rectifying barrier, in view of the subsequent wire bonding of the device (performed with aluminium thin wires). Ohmic contact formation was made on the back-side of the wafer by a triple evaporation of titanium, nickel and silver, necessary for successive bonding of the device. The fabricated devices are then packaged in a standard commercial package (TO220) in order to test electrical performances in standard circuit configuration.

The fabricated devices were then characterized by current-voltage (I-V) and capacitance-voltage (C-V) measurements. From the fitting of the I-V and C-V curves it is possible to extrapolate the values of Schottky barrier height, ideality factor, saturation current density, doping concentration of the epitaxial layer and reverse current at 600V.
The electrical characterization versus temperature was also performed on selected, packaged SBD diodes with Ti and Mo Schottky barriers, in the temperature range from 77 to 450 K.
From the analysis of the I-V curves in this temperature range, it was possible to observe a nearly-ideal behaviour of the Ti SBDs, according to the thermionic emission theory. In this way, it was possible to conclude that the Ti/4H-SiC Schottky barrier was very homogenous, and a direct estimation of the Richardson constant (A*) for 4H-SiC was also obtained. The study of the Mo SBDs I-V and C-V characteristics acquired from 77 to 450K provided a direct evidence of a deviation from the ideal behaviour expected from the thermionic emission theory. This fact can be explained by assuming a non-uniform Mo/4H-SiC interface, giving rise to Schottky barrier inhomogeneities. Further electrical and structural characterization are currently in progress in order to better under stand the electrical transport behaviours of the Mo/4H-SiC interface.

In the framework of the research project with Vishay Semiconductor Italiana S.p.A, 4H-SiC based Junction Barrier Schottky diodes (JBS) were fabricated and characterized.
Forward I-V characteristics of a JBS are very close to those of a SBD, while the I-V reverse characteristics are similar to those of p-n junctions with low leakage currents. With respect to a SBD, a JBS is characterized by a grid of p-n junctions alternated with Schottky contacts in the same active area (i.e. the area of the device where the metal/semiconductor contact is present). The JBS design is particularly effective in order to suppress excessive electric field crowding at the metal/semiconductor interface, thus reducing the leakage currents of the "pure" Schottky components of a JBS. Furthermore, the JBS is much more stable than SBD against surge overload currents, which can lead to the SBD failure.
The JBS fabrication follows the same steps of the SBD, starting from 3" 4H-SiC, n-doped wafers with an epilayer also n-doped. The main difference between the two types of devices is a further ion implantation step needed in order to obtain the p-n junctions in the JBS active area. Ion implantation of boron and aluminum was thus performed, followed by a RTP at temperatures exceeding 1550°C (in order to promote a complete electrical activation of the dopants and lattice damage recovery). The other process steps are similar to those followed for the SBD fabrication.